The Lyceum: Semiconductor Weekly — Jul 15, 2026

The world's biggest HBM maker just pulled off the largest foreign-company share sale in U.S. history — and then watched its Seoul stock crater 15% over the next three sessions. That whiplash is the week in miniature: AI demand is structurally real, but the market has started asking whether the supply buildout is racing ahead of the money that funds it. Meanwhile, the bottleneck keeps moving — from wafers to packaging to the outsourced assemblers now hiking capex to catch up.

• SK Hynix ADRs (SK Hynix): American depositary receipts began trading on Nasdaq on July 10, opening at $170 against a $149 offering price. The $26.5 billion raise is the largest first-time U.S. share sale ever by a foreign company.
• ElevATE Semiconductor acquisition (Diodes Incorporated): Definitive agreement signed for $250 million all-cash, adding analog and mixed-signal ICs used inside automated test equipment.
• Odisha glass-core substrate MoU (India MeitY / Intel / 3D Glass Solutions): India's electronics ministry confirmed the advanced-packaging substrate facility agreement, Intel's first significant participation in Indian chip manufacturing beyond design.

One image captures the current mood in chip markets: SK Hynix rings the Nasdaq opening bell on July 10, its ADRs pop to $170, and its Seoul-listed stock falls roughly 15% over the next three sessions.

The raise itself is history. SK Hynix pulled in $26.5 billion in its American depositary receipt offering — ADRs are U.S.-traded certificates representing shares in a foreign company — surpassing the $25 billion Alibaba raised in 2014. Demand outstripped supply more than seven to one, with about $5 billion going to three cornerstone investors: Baillie Gifford, Coatue Management, and Situational Awareness Partners. The company plans to spend the proceeds expanding DRAM wafer capacity, advanced packaging, and leading-edge equipment including EUV scanners. The strategic logic is clean: SK Hynix holds a 56.4% share of the HBM market — the stacked memory that sits beside every AI accelerator — and it's funding the full stack, not one slice. (SK Hynix Nasdaq debut: ADR opens at $170 after $26.5B offering)

The Seoul selloff wasn't a verdict on the business — it was dilution math colliding with broader anxiety. New shares mean existing holders own less; the drop also reflects a market that's run hard on AI optimism and now wonders whether the next leg is already priced in. According to Korean market coverage, the ADR itself fell roughly 9% over the following sessions, back near its offering price. The signal to watch is whether the ADR holds above $149. Sustained above it, U.S. investors are treating this as a structural HBM position. A durable break below, and the memory sector's sentiment problem gets real.

The chip that powers your AI assistant doesn't just get fabricated — it gets assembled. That assembly step is now the tightest constraint in the entire AI supply chain.

Digitimes reported on July 10 that TSMC's CoWoS monthly output is now being discussed at at least 200,000 wafers in 2027. CoWoS — Chip-on-Wafer-on-Substrate — is the 2.5D packaging that physically connects a GPU die to its HBM stacks on a silicon interposer. Every Nvidia H100, H200, and B200 requires it. Per Silicon Analysts' capacity tracking, TSMC is on track for 120,000–130,000 wafer starts per month by end-2026, up from just 13,000 at end-2023 — roughly a 10x expansion in three years. TrendForce reports the supply-demand gap is expected to narrow from around 20% today to about 10% by year-end. (TSMC’s CoWoS expansion is getting big enough to drag the whole packaging tool ch)

The tell isn't the headline number. It's that equipment suppliers are still waiting for TSMC to finalize order allocation this late in the move-in sequence — which means the capex wave hasn't fully hit vendor books yet. When it does, it will show up in Applied Materials, Lam Research, and Tokyo Electron guidance. Watch for that allocation to keep slipping: if it does, it stops looking like a clean ramp and starts looking like demand still outrunning the plumbing.

The transistor has been getting flatter for sixty years. Samsung just showed it can go vertical.

At the 2026 VLSI Symposium (June 14–18), Samsung's Semiconductor Research Center presented the first demonstration of 3D-stacked FETs at a 42nm gate pitch using triple-stacked nanosheet channels. A 3D Stacked FET — also called a CFET — stacks the two transistors in a logic pair directly atop each other instead of side by side, roughly doubling density in the same footprint. The paper scored 8.29 out of 10 and won Best Paper among more than 1,000 submissions. Samsung says it tackled the hard problems — power delivery, uniformity, electrical interference — using advanced epitaxial growth and a precise insulating structure called Middle Dielectric Isolation.

Here's the honest read: a Best Paper doesn't fix a fab. Samsung's foundry has bled yields and customers as its gap with TSMC widened. This is world-class transistor research; whether it becomes a manufacturable, customer-winning node is the separate, harder question — probably five-plus years from high-volume manufacturing. The observable signal will be whether Samsung's foundry roadmap starts naming a CFET node with a date attached, or whether this stays a trophy on the research shelf. (Samsung Builds the Industry's Smallest 3D-Stacked Transistor and Wins VLSI Best )

On July 10, the U.S. Bureau of Industry and Security issued a rule revising licensing policy for semiconductor exports to China — and the direction is one-way. (BIS tightens AI chip and fab‑equipment export licensing for China)

Per the BIS release, Nvidia's H200, AMD's MI325X, and similar accelerators move from near-automatic denial to case-by-case review, but only if applicants prove compliance, U.S.-based security testing, and no reduction in capacity available to American customers. In the same rule, BIS closed a loophole that had let certain foreign firms ship semiconductor manufacturing equipment into China without a license, and stated plainly it does not intend to approve licenses that expand capacity or upgrade technology at Chinese fabs. New license requirements also hit foundries and packaging houses exporting advanced chips unless they meet tight conditions on who designed the chip and where it's packaged. (BIS tightens AI chip and fab‑equipment export licensing for China)

The practical effect: any new AI GPU, HBM, or leading-edge logic capacity in China now starts from a default of "no." That pushes multinationals to park real expansions in Korea, Taiwan, and allied Southeast Asia — and forces OSATs to reroute through "trusted" designers and locations rather than lowest-cost flows. This is high-confidence because it comes straight from BIS primary text. The signal to watch is disclosure: which packaging players first admit, in filings, that they're re-qualifying supply chains to stay compliant.

The cleanest early signal this week may not be TSMC — it's ASE.

Per a July 13 Digitimes roundup, ASE raised 2026 capital spending to $8.5 billion from $7 billion and is building 15 plants, while Hanmi Semiconductor's 2.5D TC Bonder 40 — built for TSMC's CoWoS flow — is expected to land at ASE as it leans harder into CoWoS-related expansion. ASE sits in an awkward, useful spot: close enough to customers to feel real order pressure, but downstream enough that it usually moves only after foundry promises turn into packaging pain.

Paired with TSMC's still-tight CoWoS chatter and the widening handoff to ASE, SPIL, and Amkor, this looks like the constraint spreading into the outsourced packaging layer — which means capacity resilience for AI hardware now depends on more than one company's move-in schedule. The caveat: this is trade-press reporting, not a filing, so treat the exact spending figure as firmer than any implied utilization timeline. Watch whether SPIL and Amkor follow with their own capex hikes — that would confirm packaging, not wafers, is now the leading edge of the buildout.

This week: a Korean memory giant that soared in New York and sank in Seoul on the same shares, a Best Paper trophy sitting in a foundry that can't win customers, and a $26,955 government wafer order that tells you more about real capacity than most billion-dollar press releases. Somewhere in that spread is the whole industry — flush with capital, starved for packaging slots, and quietly wondering whether the helium holds out before the CoWoS tools even arrive.

Stay skeptical of the headline number and long the plumbing.

Forward this to the procurement lead who still thinks the bottleneck is wafers.